Wafers composed of semiconductor material (semiconductor wafers), as substrates for particularly demanding components such as those, for example, having a minimum structural length of ≤22 nm, that is to say 22 nm design rule according to ITRS (“International Technology Roadmap for Semiconductors”), have to be particularly flat.
In accordance with the prior art, the wafers sawn from a single crystal of semiconductor material are planarized in various work steps.                mechanical wafer processing (lapping, grinding),        chemical wafer processing (alkaline or acidic etch),        chemomechanical wafer processing: single-side polishing (SSP), double-side polishing (DSP), single-side haze-free or mirror polishing using a soft polishing pad (chemical mechanical polishing, CMP).        
The mechanical processing of the semiconductor wafers serves primarily for the global leveling of the semiconductor wafer, furthermore for the thickness calibration of the semiconductor wafers, and also for the removal of the crystalline-damaged surface layer and processing traces (sawing grooves, incision mark) caused by the preceding separation process.
In the case of etching, contaminants and/or native oxides are removed chemically from the surface of the semiconductor wafers.
Final smoothing of the surfaces of the semiconductor wafer is finally effected by means of chemical mechanical polishing.
In the case of single-side polishing (SSP), semiconductor wafers are held during processing on the rear side on a support plate by means of wax, by vacuum or by means of adhesion and are subjected to polishing on the other side.
A suitable single-side polishing machine is disclosed in the document U.S. Pat. No. 6,116,997 A, for example.
In the case of traditional double-side polishing (DSP), semiconductor wafers are inserted loosely into suitably dimensioned cutouts in a thin carrier plate and are polished on the front and rear sides simultaneously in a “freely floating” manner between an upper and a lower polishing plate each covered with a polishing pad.
This polishing method is effected with the supply of a polishing agent slurry usually based on a silica sol. In the case of DSP, the front and rear sides of the semiconductor wafer are simultaneously polished at the same time.
A suitable double-side polishing machine is disclosed in the application DE 100 07 390 A1, for example.
A corresponding DSP method is described in the patent specification U.S. Pat. No. 3,691,694, for example.
In accordance with an embodiment of DSP as described in the patent specification EP208315B1, semiconductor wafers in carrier plates composed of metal or plastic, which have suitably dimensioned cutouts, are moved between two rotating polishing plates covered with a polishing pad in the presence of a polishing agent on a path predetermined by the machine and process parameters and are thereby polished (the term “carrier plates” is employed in the literature).
The DSP is usually carried out using a polishing pad composed of homogeneous, porous polymer foam, as described in the document DE10004578C1, for example.
Different polishing pads each having specific properties can be used depending on the polishing process to be carried out and the respectively desired material removal from the surface or surfaces of the semiconductor wafer.
Polishing pads can consist of a thermoplastic or thermosetting polymer. As material for these pads, referred to as foamed polishing pads (foamed pads), a multiplicity of materials come into consideration, e.g. polyurethanes, polycarbonate, polyamide, polyacrylate, polyester, etc. A polishing pad produced from a polymer is disclosed in US 2008/0102741 A1, for example.
However, polishing pads can also consist of foamed plates or felt or fibrous substrates impregnated with polymers (non-woven pad). Such a pad is described in U.S. Pat. No. 5,510,175 A, for example.
In principle, it possible to differentiate between, for example, polishing pads which contain no bonded abrasives in their surface and those which contain bonded abrasives. These polishing pads are designated as fixed abrasive pads (FA pads).
Polishing pads which contain no bonded abrasives are disclosed in the European patent application EP 2 266 757 A1, for example.
Polishing pads which contain bonded abrasives are disclosed in the application US 2005 0 227 590 A1, for example. U.S. Pat. No. 5,958,794 teaches a method for the treatment of a substrate surface composed of semiconductor material using a pad which contains bonded abrasives.
A further differentiating feature of polishing pads is the hardness of the respective polishing pad, for example. Harder polishing pads are less compressible than softer polishing pads, but have the disadvantage that during polishing damage can occur in the polished surface of the semiconductor wafer since loose particles cannot press into the pad.
Conditioning (refreshing) of the polishing pad used for the polishing of semiconductor wafers becomes necessary if, for example, the geometry of the polishing pad surface has changed or too many solids have been incorporated on the surface of the polishing pad (glazing). As a result of the incorporated solids, there is a lasting change in the polishing pad properties, and so firstly the specific polishing removal rate is adversely influenced and secondly a non-uniform polishing removal can take place.
The double-side polishing methods known in the prior art have the disadvantage that generally the amount of material removed is higher in the edge region of the wafer composed of semiconductor material than in the other regions of the wafer (edge roll-off, ERO) and thus lead to a poor edge geometry.
The severity of the edge roll-off depends, inter alia, on how far the wafer sinks in the polishing pad and the edge is thereby rounded. The prior art describes various measures for reducing or avoiding the edge roll-off during the polishing process.
Xin reports the use of harder polishing pads for improving the flatness of silicon wafers (Xin, Y. B. 1998, Modeling of Pad-wafer contact pressure distribution in chemical mechanical polishing, International Journal for Manufacturing Science and Technology, v.1, n.2, pp.20-34). This study shows that the pressure on the edge region of a wafer composed of semiconductor material is higher approximately by a factor of 1.5 in the case of a very soft pad than in the case of a very hard pad.
The document EP 2 345 505 A2 teaches the adaptation of the surface shape of a polishing pad by corresponding dressing in such a way that the semiconductor wafer has the desired surface shape after the polishing process.
The American patent U.S. Pat. No. 7,364,495 B2 teaches a device and a method for simultaneously polishing the front side and the rear side of a semiconductor wafer, wherein the desired surface shape of the semiconductor wafer is achieved during polishing by means of slight alterations (μm range) of the polishing plate geometry. According to U.S. Pat. No. 7,364,495 B2, the polishing plate geometry can be obtained for example by changing the polishing plate temperature, but also mechanically by means of corresponding pressure units.
The application US 2003/0224604 A1 describes a method for avoiding edge roll-off by using a sacrificial ring which encloses the semiconductor wafer during polishing and thus protects the edge region of the wafer against increased material removal, since the circumference of the semiconductor wafer is extended. In this case, the ring produced from silicon or ceramic has the thickness of the semiconductor wafer to be polished.
What is disadvantageous about the method described in the published patent application US 2003/0224604 A1 is, inter alia, that the edge of the semiconductor wafer can be damaged by the surrounding ring by the forces occurring during the polishing process.
The European patent application EP 1 852 899 A1 describes a method for avoiding edge roll-off wherein, after double-side polishing of a semiconductor wafer, one or both sides of the semiconductor wafers is/are protected with a resin film before edge polishing is carried out. The protection film is subsequently removed again using an aqueous alkaline solution, for example.
Other methods for avoiding edge roll-off during the polishing of a semiconductor wafer are directed to the use of specific polishing pads and/or the dressing of the polishing pad.
By way of example, the published European patent application EP 2 345 505 A2 describes a method for dressing a polishing pad, wherein the profile of a polishing pad bearing on a polishing plate is measured and the polishing parameters for obtaining the desired surface properties of the semiconductor wafer are selected on the basis of this measurement. In addition, the surface of the measured polishing pad can also be modified by a corresponding dressing process.
The U.S. Pat. No. 6,682,405 B2 teaches methods for dressing a polishing pad using a ring-shaped tool whose surface that comes into contact with the polishing pad surface, contrary to the prior art, is inclined toward the polishing pad surface, as a result of which a constant pressure is obtained during the polishing pad dressing.
The published German patent application DE 10 2008 056 276 A1 teaches a method for regulating the working gap of a double-side polishing machine. Said working gap, in which the substrate to be polished is situated, is formed by an upper and a lower polishing plate each covered with a polishing pad (working surface). At least one polishing plate can be deformed by an adjusting device, such that the shape of the working gap changes and the working surfaces have a maximum parallelism. Material removal that is as uniform as possible is intended to be ensured by the regulation of the working gap geometry.
Furthermore, DE 10 2008 056 276 A1 discloses regulating the working gap in such a way that, for example, a specific concavity or convexity of one or both polishing plates is obtained, wherein the working gap can have a different height on one side than on the other side.
The method for regulating the working gap of a double-side polishing machine as taught in the published patent application DE 10 2008 056 276 A1 presupposes corresponding technical devices that are not always available. Furthermore, edge roll-off cannot always be avoided even with absolute parallelism of the polishing plates, since said edge roll-off is not just influenced by the parallelism of the polishing plates.